VLSI Projects - -
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1 2017 A Novel Area-Efficient VLSI ArchitectureFor Recursion Computation In LTETurbo Decoders coming soon
2 2017 Design A DSP Operations Using Vedic Mathematics coming soon
3 2017 A Novel Approach For Parallel CRC Generation For High Speed Application coming soon
4 2017 An Efficient Implementation Of Floating Point Multiplier coming soon
5 2017 Design And Implementation Of Carry Select Adder Without Using Multiplexers coming soon
6 2017 32-bit decimalmatrix with sram coming soon
7 2017 A High Speed Binary Floating Point Multiplier Using Dadda Algorithm coming soon
8 2017 Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach coming soon
9 2017 Trade-Offs for Threshold ImplementationsIllustrated on AES coming soon
10 2017 Efficient Coding Schemes for Fault-TolerantParallel Filters coming soon
11 2017 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication coming soon
12 2017 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks coming soon
13 2017 Implementation of High Speed Low Power Combinational and Sequential Circuits using Reversible logic coming soon
14 2017 A Decimal Binary Multi-operand Adder using a Fast Binary to Decimal Converter coming soon
15 2017 Low-Power and Area-Efficient Shift Register Using Pulsed Latches coming soon
16 2017 Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” coming soon
17 2017 Fully Reused VLSI Architecture ofFM0Manchester Encoding Using SOLS coming soon
18 2017 A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications coming soon
19 2017 3 input xor or xnor gate coming soon
20 2017 Design Of high Performance 64 Bit MAC Unit coming soon
21 2017 Multi operand Redundant Adders on FPGAs . coming soon
22 2017 high speed convolution and deconvolution algorithm coming soon
23 2017 Design and Analysis of Approximate Compressors for Multiplication coming soon
24 2017 Low-Power Programmable PRPG With Test Compression Capabilities coming soon
25 2017 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay coming soon
26 2017 Area-Delay Efficient Binary Adders in QCA coming soon
27 2017 Split SAR ADCs Improved Linearity With Power and Speed Optimization coming soon
28 2017 A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL coming soon
29 2017 A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving coming soon
30 2017 Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping 5000 coming soon
31 2017 Reliability Enhancement of Low-power sequential circuits using reconfigurable Pulsed Latches 5000 coming soon
32 2017 Design for testability of sleep convention logic 5000 coming soon
33 2017 LFSR-Based Generation of Multi cycle Tests 5000 coming soon
34 2017 Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 5000 coming soon
35 2017 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding 5000 coming soon
36 2017 A Bit plane Decomposition Matrix Based VLSI Integer Transform Architecture for HEVC 5000 coming soon
37 2017 Low Complexity and Critical Path based VLSI Architecture for LMS Adaptive Filter using Distributed Arithmetic 5000 coming soon
38 2017 Probabilistic Error Modeling for Approximate Adders 5000 coming soon
39 2017 Fault Space Transformation: A Generic Approach to Counter Differential Fault Analysis and Differential Fault Intensity Analysis on AES-like Block Ciphers 5000 coming soon
40 2017 Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit 5000 coming soon
41 2017 Efficient RNS Scalers for the Extended Three-Moduli Set (2n -1; 2n+p; 2n + 1) 5000 coming soon
42 2017 Reconfigurable Constant Multiplication for FPGAs 5000 coming soon
43 2017 DLAU: A Scalable Deep Learning Accelerator Uniton FPGA 5000 coming soon
44 2017 Optimization of Constant Matrix Multiplication with Low Power and High Throughput 5000 coming soon
45 2017 An Optimized 3x3 Shift and Add Multiplier on FPGA 5000 coming soon
46 2017 Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm 5000 coming soon
47 2017 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing 5000 coming soon
48 2017 RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder 5000 coming soon
49 2017 Probabilistic Error Analysis of Approximate Recursive Multipliers 5000 coming soon
50 2017 Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor 5000 coming soon
51 2017 On the Implementation of Computation-in-Memory Parallel Adder 5000 coming soon
52 2017 Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction 5000 coming soon
53 2017 High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder 5000 coming soon
54 2017 High Performance Parallel Decimal Multipliers using Hybrid BCD Codes 5000 coming soon
55 2017 Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression 5000 coming soon
56 2017 Design and Analysis of Multiplier Using Approximate 15-4 Compressor 5000 coming soon
57 2017 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication 5000 coming soon
58 2017 Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic 5000 coming soon
59 2017 Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems 5000 coming soon
60 2017 DSP48E Efficient Floating Point Multiplier Architectures on FPGA 5000 coming soon
61 2017 Fast Energy Efficient Radix-16 Sequential Multiplier 5000 coming soon
62 2017 A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n− 1, 2n+ 1, 22n+ 1, 22n+p} 5000 coming soon
63 2017 Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity 5000 coming soon
64 2017 Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx 5000 coming soon
65 2017 Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing 5000 coming soon
66 2017 Design of Power and Area Efficient Approximate Multipliers 5000 coming soon
67 2017 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers 5000 coming soon
68 2017 A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers 5000 coming soon
69 2017 A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation 5000 coming soon
70 2016 Design of high speed multiplier using Modified Booth Algorithm with hybrid carry look-ahead adder 4000 coming soon
71 2016 An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA 4000 coming soon
72 2016 Energy-Aware Scheduling of FIR Filter Structures using a Timed Automata Model 4000 coming soon
73 2016 Design Of High Speed Multiplier Using Modified Booth Algorithm With Hybrid Carry Look-Ahead Adder 4000
74 2016 Design Of Low Power, High Performance 2-4 And 4-16 Mixed-Logic Line Decoders 4000
75 2016 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels 4000
76 2016 Design of Register File using Reversible Logic 4000 coming soon
77 2016 Low-Quantum Cost Circuit Constructions for Adder and Symmetric Boolean Functions 4000 coming soon
78 2016 Squaring in Reversible Logic using Zero Garbage and Reduced Ancillary inputs 4000 coming soon
79 2016 Improved Synthesis of Reversible Sequential Circuits 4000 coming soon
80 2016 A Low-Power Robust Easily Cascaded Pentamtj-Based Combinational And Sequential Circuits 4000 coming soon
81 2016 Low-Power Ask Detector For Low Modulation Indexes And Rail-To-Rail Input Range 4000 coming soon
82 2016 A Low-Power Incremental Delta–Sigma Adc For Cmos Image Sensors 4000 coming soon
83 2016 A 55-Ghz-Bandwidth Track-And-Hold Amplifier In 28-Nm Low-Power Cmos 4000 coming soon
84 2016 A Low Power Trainable Neuromorphic Integrated Circuit That Is Tolerant To Device Mismatch 4000 coming soon
85 2016 Pns-Fcr: Flexible Charge Recycling Dynamic Circuit Technique For Low-Power Microprocessors 4000 coming soon
86 2016 Low-Power Variation-Tolerant Nonvolatile Lookup Table Design 4000 coming soon
87 2016 Dual Use Of Power Lines For Design-For-Testability—A Cmos Receiver Design 4000
88 2016 A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory 4000 coming soon
89 2016 Arithmetic algorithms for extended precision using floating-point expansions 4000 coming soon
90 2016 Hybrid Lut/Multiplexer Fpga Logic Architectures 4000
91 2016 Hardware And Energy-Efficient Stochastic Lu Decomposition Scheme For Mimo Receivers 4000 coming soon
92 2016 Input-Based Dynamic Reconfiguration Of Approximate Arithmetic Units For Video Encoding 4000
93 2016 High-Speedand Energy-Efficient Carry Skip Adder Operating Under A Wide Rangeof Supply Voltage Levels 4000 coming soon
94 2016 VLSI Design for Convolutive Blind Source Separation 4000 coming soon
95 2016 A High-Speed FPGA Implementation of an RSD-Based ECC Processor 4000 coming soon
96 2016 Low-Cost High-Performance Vlsi Architecture For Montgomery Modular Multiplication 4000
97 2016 High Speed Hybrid Double Multiplication Architectures Using New Serial-Out Bit- Level Mastrovito Multipliers 4000 coming soon
98 2016 A Normal I/O Order Radix-2 Fft Architecture To Process Twin Data Streams For Mimo 4000 coming soon
99 2016 A Cellular Network Architecture With Polynomial Weight Functions 4000 coming soon
100 2016 A Modified Partial Product Generator For Redundant Binary Multipliers 4000 coming soon
101 2016 A High Throughput List Decoder Architecture for Polar Codes 4000 coming soon
102 2016 A Novel Coding Scheme For Secure Communications In Distributed Rfid Systems 4000 coming soon
103 2016 Design for Testability of Sleep Convention Logic 4000 coming soon
104 2016 Memory-Reduced Turbo Decoding Architecture Using Nii Metric Compression 4000 coming soon
105 2016 An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code 4000 coming soon
106 2016 Low-Power Parallel Chien Search Architecture Using A Two-Step Approach 4000 coming soon
107 2016 Fault Tolerant Parallel Ffts Using Error Correction Codes And Parseval Checks 4000
108 2016 Concept, Design, And Implementation Of Reconfigurable Cordic 4000
109 2016 On Efficient Retiming Of Fixed-Point Circuits 4000 coming soon
110 2016 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits 4000
111 2016 A High-Performance Fir Filter Architecture For Fixed And Reconfigurable Applications 4000
112 2016 Flexible Dsp Accelerator Architecture Exploiting Carry-Save Arithmetic 4000 coming soon
113 2016 Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation 4000
114 2016 Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding 4000
115 2015 Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications 3000
116 2015 RECURSIVE APPROACH TO THE DESIGN OF A PARALLEL SELF-TIMED ADDER 2000
117 2015 A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL 3000
118 2015 LOW-POWER AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES 3000
119 2015 High Speed Convolution And Deconvolution Algorithm Based On Ancient Indian Vedic Mathematics 3000
120 2015 A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler 3000 coming soon
121 2015 A GENERALIZED ALGORITHM AND RECONFIGURABLE ARCHITECTURE FOR EFFICIENT AND SCALABLE ORTHOGONAL APPROXIMATION OF DCT 3000 coming soon
122 2015 DESIGN AND IMPLEMENTATION OF AREA-OPTIMIZED AES BASED ON FPGA 3000 coming soon
123 2015 RECURSIVE APPROACH TO THE DESIGN OF A PARALLEL SELF-TIMED ADDER 3000
124 2015 Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology 3000 coming soon
125 2015 RELIABLE AND ERROR DETECTION ARCHITECTURES OF POMARANCH FOR FALSE-ALARM-SENSITIVE CRYPTOGRAPHIC APPLICATIONS 3000 coming soon
126 2015 A NOVEL AREA-EFFICIENT VLSI ARCHITECTURE FOR RECURSION COMPUTATION IN LTE TURBO DECODERS 3000 coming soon
127 2015 NON-BINARY ORTHOGONAL LATIN SQUARE CODES FOR A MULTILEVEL PHASE CHARGE MEMORY (PCM) 3000 coming soon
128 2015 LOW-POWER PROGRAMMABLE PRPG WITH TEST COMPRESSION CAPABILITIES 3000 coming soon
129 2015 LOW-POWER AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES 3000 coming soon
130 2015 A LOW-POWER HYBRID RO PUF WITH IMPROVED THERMAL STABILITY FOR LIGHT WEIGHT APPLICATIONS 3000 coming soon
131 2015 Area-Efficient Fixed-Width Squarer with Dynamic Error-Compensation Circuit 3000 coming soon
132 2015 A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory 3000 coming soon
133 2014 A Decimal / Binary Multi-operand Adder using a Fast Binary to Decimal Converter 2000
134 2014 Design and Development of FPGA Based Low Power Pipelined 64-Bit RISe Processor with Double Precision Floating Point Unit 2000
135 2014 Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” 2000
136 2014 A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving 2000