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VERILOG HDL

 Introduction to Verilog HDLØ
 Modeling ConceptsØ
 Gate Level Modelingv
 Data Flow Modelingv
 Behavioural Modelingv
 Structural Modelingv
 Switch Level Modelingv
 Data TypesØ
 OperatorsØ
 Procedure and Flow Of Control StatementØ
 Designing of Combinational CircuitsØ
 Designing of Sequential CircuitsØ
 FSM Design ModelingØ
 Designing of MemoriesØ
 Writing Testbench using VerilogØ
 Task and FunctionsØ
 System TasksØ
 Compiler DirectivesØ
 Advance Nets in VerilogØ
 Bus Functional ModelingØ
 Verilog Based AssertionsØ
 Code Coverage.Ø

 

PHYSICAL DESIGN

 Trends And Challenges In VLSIØ
 ASIC FlowØ
 Introduction of TransistorsØ
 Introduction of CMOS TechnologyØ
 Stick DiagramsØ
 Lambda – RulesØ
 LayoutsØ

 

STA (STATIC TIMING ANALYSIS)

 Fundamentals of Delay calculations (wire modeling).Ø
 Setup/Hold Time definitionsØ & Slack Calculations.
 Different Timing Path Analysis.
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 AnalysisØ & approach to minimize the timing violations.
 STA Constraint development.
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PLACE & ROUTE

 Floor PlanningØ
 I/O RingØ & Power Grid Planning
 Placement Methodologies
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 CTS(Clock Tree Synthesis)Ø
 RoutingØ & Timing Optimization

LOGIC DESIGN

 FSM DesignØ & FIFO Design
 Handshaking Protocol’s
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 Math Function ImplementationØ
 Reset DesignØ
 Clock ManagementØ

EDA TOOLS

Micro Wind – LayoutØ
 DSCH – SchematicsØ
 H-SpiceØ & Spice Language(optional)